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| TC58128AFTI TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 128-MBIT (16M x 8 BITS) CMOS NAND E PROM DESCRIPTION The TC58128A is a single 3.3 V 128-Mbit (138,412,032) bit NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as 528 bytes x 32 pages x 1024 blocks. The device has a 528-byte static register which allows program and read data to be transferred between the register and the memory cell array in 528-byte increments. The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes: 528 bytes x 32 pages). The TC58128A is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage. FEATURES * Organization Memory cell allay 528 x 32K x 8 Register 528 x 8 Page size 528 bytes Block size (16K + 512) bytes Modes Read, Reset, Auto Page Program Auto Block Erase, Status Read Mode control Serial input/output Command control * * * * Power supply VCC = 2.7 V to 3.6 V Program/Erase Cycles 1E5 cycle (with ECC) Access time Cell array to register 25 s max Serial Read Cycle 50 ns min Operating current Read (50 ns cycle) 10 mA typ. Program (avg.) 10 mA typ. Erase (avg.) 10 mA typ. Standby 100 A Package TSOPI48-P-1220-0.50 (Weight: 0.53 g typ.) * * * PIN ASSIGNMENT (TOP VIEW) NC NC NC NC NC GND RE CE NC NC VCC VSS NC NC CLE ALE WE WP NC NC NC NC NC PIN NAMES 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC NC NC I/O8 I/O7 I/O6 I/O5 NC NC NC VCC VSS NC NC NC I/O4 I/O3 I/O2 I/O1 NC NC NC NC I/O1 to I/O8 CE RY / BY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 I/O port Chip enable Write enable Read enable Command latch enable Address latch enable Write protect Ready/Busy Ground input Power supply Ground 000707EBA1 WE RE CLE ALE WP RY/BY GND VCC VSS * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice. 2001-05-30 1/33 TC58128AFTI BLOCK DIAGRAM VCC VSS Status register I/O1 to I/O8 I/O Control circuit Address register Column buffer Column decoder Command register Data register Sense amp Row address decoder CE CLE ALE WE RE WP RY/BY RY/BY Logic control Control Row address buffer decoder Memory cell array HV generator ABSOLUTE MAXIMUM RATINGS SYMBOL VCC VIN VI/O PD Tsolder Tstg Topr Power Supply Voltage Input Voltage Input/Output Voltage Power Dissipation Soldering Temperature (10s) Storage Temperature Operating Temperature RATING VALUE -0.6 to 4.6 -0.6 to 4.6 -0.6 V to VCC + 0.3 V ( 4.6 V) 0.3 260 -55 to 150 -40 to 85 UNIT V V V W C C C CAPACITANCE *(Ta = 25C, f = 1 MHz) SYMB0L CIN COUT * Input Output PARAMETER CONDITION VIN = 0 V VOUT = 0 V MIN MAX 10 10 UNIT pF pF This parameter is periodically sampled and is not tested for every device. 2001-05-30 2/33 TC58128AFTI VALID BLOCKS (1) SYMBOL NVB PARAMETER Number of Valid Blocks MIN 1004 TYP. MAX 1024 UNIT Blocks (1) The TC58128A occasionally contains unusable blocks. Refer to Application Note (14) toward the end of this document. RECOMMENDED DC OPERATING CONDITIONS SYMBOL VCC VIH VIL * PARAMETER Power Supply Voltage High Level input Voltage Low Level Input Voltage -2 V (pulse width lower than 20 ns) MIN 2.7 2.0 -0.3* TYP. 3.3 MAX 3.6 VCC + 0.3 0.8 UNIT V V V DC CHARACTERISTICS (Ta = - 40 to 85C, VCC = 2.7 V to 3.6 V) SYMBOL IIL ILO ICCO1 ICCO3 ICCO4 ICCO5 ICCO7 ICCO8 ICCS1 ICCS2 VOH VOL IOL ( RY/BY ) PARAMETER Input Leakage Current Output Leakage Current Operating Current (Serial Read) Operating Current (Command Input) Operating Current (Data Input) Operating Current (Address Input) Programming Current Erasing Current Standby Current Standby Current High Level Output Voltage Low Level Output Voltage Output Current of RY/BY pin CE = VIH CE = VCC - 0.2 V CONDITION VIN = 0 V to VCC VOUT = 0.4 V to VCC CE = VIL, IOUT = 0 mA, tcycle = 50 ns MIN TYP. 10 10 10 10 10 10 8 MAX 10 10 30 30 30 30 30 30 1 100 0.4 UNIT A A mA mA mA mA mA mA mA A V V mA tcycle = 50 ns tcycle = 50 ns tcycle = 50 ns 2.4 IOH = -400 A IOL = 2.1 mA VOL = 0.4 V 2001-05-30 3/33 TC58128AFTI AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (Ta = - 40 to 85C, VCC = 2.7 V to 3.6 V) SYMBOL tCLS tCLH tCS CLE Setup Time CLE Hold Time PARAMETER MIN 0 10 MAX UNIT ns ns NOTES CE Setup Time CE Hold Time Write Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time 0 10 25 0 10 20 10 50 ns ns ns ns ns ns ns ns tCH tWP tALS tALH tDS tDH tWC tWH WE High Hold Time WP High to WE Low Ready to RE Falling Edge Read Pulse Width Read Cycle Time RE Access Time (Serial Data Access) CE High Time for Last Address in Serial Read Cycle RE Access Time (ID Read) Data Output Hold Time RE High to Output High Impedance CE High to Output High Impedance RE High Hold Time Output-High-impedance-to- RE Rising Edge RE Access Time (Status Read) CE Access Time (Status Read) RE High to WE Low WE High to CE Low WE High to RE Low ALE Low to RE Low (ID Read) CE Low to RE Low (ID Read) Memory Cell Array to Starting Address WE High to Busy ALE Low to RE Low (Read Cycle) RE Last Clock Rising Edge to Busy (in Sequential Read) CE High to Ready (When interrupted by CE in Read Mode) Device Reset Time (Read/Program/Erase) 15 100 20 35 50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s tWW tRR tRP tRC tREA tCEH tREAID tOH tRHZ tCHZ tREH tIR tRSTO tCSTO tRHW tWHC tWHR tAR1 tCR tR tWB tAR2 tRB tCRY tRST 35 100 (2) 35 10 30 20 15 0 35 45 0 30 30 100 100 25 200 ns ns ns s s 50 200 1+ tr ( RY/BY ) 6/10/500 (1) (2) AC TEST CONDITIONS PARAMETER Input level Input pulse rise and fall time Input comparison level Output data comparison level Output load CONDITION 2.4 V, 0.4 V 3 ns 1.5 V, 1.5 V 1.5 V, 1.5 V CL (100 pF) + 1 TTL 2001-05-30 4/33 TC58128AFTI Note: (1) CE High to Ready time depends on the pull-up resistor tied to the RY/ BY pin. (Refer to Application Note (9) toward the end of this document.) (2) Sequential Read is terminated when tCEH is greater than or equal to 100 ns. If the RE to CE delay is less than 30 ns, RY/ BY signal stays Ready. tCEH 100 ns * CE *: VIH or VIL RE 525 RY/BY 526 527 A A : 0 to 30 ns Busy signal is not output. Busy tCRY PROGRAMMING AND ERASING CHARACTERISTICS (Ta = - 40 to 85C, VCC = 2.7 V to 3.6 V) SYMBOL tPROG N tBERASE PARAMETER Programming Time Number of Programming Cycles on Same Page Block Erasing Time MIN TYP. 200 to 300 2 MAX 1000 3 10 ms UNIT s (1) NOTES (1): Refer to Application Note (12) toward the end of this document. 2001-05-30 5/33 TC58128AFTI TIMING DIAGRAMS Latch Timing Diagram for Command/Address/Data CLE ALE CE RE Setup Time Hold Time WE tDS I/O1 to I/O8 tDH : VIH or VIL Command Input Cycle Timing Diagram CLE tCLS tCS tCLH tCH CE tWP WE tALS ALE tDS I/O1 to I/O8 tALH tDH : VIH or VIL 2001-05-30 6/33 TC58128AFTI Address Input Cycle Timing Diagram tCLS CLE tCS CE tWC tWC tWP WE tWH tWP tWH tWP tALS ALE tDS I/O1 to I/O8 tDH tDS tDH tDS tALH tDH A0 to A7 A9 to A16 A17 to A23 : VIH or VIL Data Input Cycle Timing Diagram tCLH CLE tCH CE tALS ALE tWP WE tWC tWH tWP tWP tDS I/O1 to I/O8 tDH tDS tDH tDS tDH DIN0 DIN1 DIN 527 : VIH or VIL 2001-05-30 7/33 TC58128AFTI Serial Read Cycle Timing Diagram tRC CE tRP RE tREH tRP tRP tCHZ tREA I/O1 to I/O8 tRR RY/BY tOH tRHZ tREA tOH tRHZ tREA tOH tRHZ Status Read Cycle Timing Diagram tCLS CLE tCLS tCS tCLH CE tWP WE tCH tWHC tWHR tCSTO tCHZ RE tOH tDS tDH tIR tRSTO Status output tRHZ I/O1 to I/O8 70H* RY/BY * 70H represents the hexadecimal number : VIH or VIL 2001-05-30 8/33 TC58128AFTI Read Cycle (1) Timing Diagram CLE tCLS tCS tCLH tCH tCEH CE tWC WE tCRY tALH ALE tALS tALH tAR2 tR RE tRR tRC tWB tDS tDH tDS tDH A0 to A7 Column address N* tDS tDH A9 to A16 tDS tDH A17toA23 tREA DOUT N DOUT N+1 DOUT N+2 DOUT 527 tRB I/O1 to I/O8 00H RY/BY * Read Operation using 00H Command N: 0 to 255 : VIH or VIL Read Cycle (1) Timing Diagram: When Interrupted by CE CLE tCLS tCS tCLH tCH CE tWC WE tCHZ tALH ALE tALS tALH tAR2 tR RE tRR tRC tWB tDS tDH tDS tDH A0 to A7 Column address N* tDS tDH A9 to A16 tDS tDH A17toA23 tREA DOUT N DOUT N+1 tOH tRHZ DOUT N+2 I/O1 to I/O8 00H RY/BY * Read Operation using 00H Command N: 0 to 255 : VIH or VIL 2001-05-30 9/33 TC58128AFTI Read Cycle (2) Timing Diagram CLE tCLS tCS tCLH tCH CE WE tALH ALE tALS tALH tAR2 tR RE tRR tRC tWB tDS tDH tDS tDH A0 to A7 A9 to A16 A17toA23 Column address N* DOUT tREA DOUT DOUT 527 I/O1 to I/O8 01H 256 + M 256 + M + 1 RY/BY * Read Operation using 01H Command N: 0 to 255 : VIH or VIL Read Cycle (3) Timing Diagram CLE tCLS tCS tCLH tCH CE WE tALH ALE tALS tALH tAR2 tR RE tRR tRC tWB tDS tDH tDS tDH A0 to A7 A9 to A16 A17toA23 Column address N* DOUT tREA DOUT DOUT 527 I/O1 to I/O8 50H 512 + M 512 + M + 1 RY/BY * Read Operation using 50H Command N: 0 to15 : VIH or VIL 2001-05-30 10/33 TC58128AFTI Sequential Read (1) Timing Diagram CLE CE WE ALE RE I/O1 to I/O8 00H A0 to A7 A9 to A16 A17toA23 Column Page address address N M tR N N+1 N+2 527 tR 0 1 2 527 RY/BY Page M access Page M + 1 access : VIH or VIL Sequential Read (2) Timing Diagram CLE CE WE ALE RE I/O1 to I/O8 01H A0 to A7 A9 to A16 A17toA23 Column Page address address N M tR 256 + 256 + 256 + N N+1 N+2 527 tR 0 1 2 527 RY/BY Page M access Page M + 1 access : VIH or VIL 2001-05-30 11/33 TC58128AFTI Sequential Read (3) Timing Diagram CLE CE WE ALE RE I/O1 to I/O8 50H A0 to A7 A9 to A16 A17toA23 Column Page address address N M tR 512 + 512 + 512 + N N+1 N+2 527 tR 512 513 514 527 RY/BY Page M access Page M + 1 access : VIH or VIL 2001-05-30 12/33 TC58128AFTI Auto-Program Operation Timing Diagram tCLS CLE tCLS tCLH tCS CE tCS WE tCH tALH tALS tALH tALS tPROG tWB ALE RE tDS tDS tDH tDS tDH A0 to A7 A9 to A16 A17toA23 tDH DIN0 DIN1 DIN 527 10H tDS tDH 70H Status output I/O1 to I/O8 80H RY/BY : VIH or VIL : Do not input data while data is being output. Auto Block Erase Timing Diagram CLE tCLS tCS CE tCLH tCLS WE tALS ALE tALH tWB tBERASE RE tDS tDH I/O1 to I/O8 60H A9 to A16 A17toA23 D0H 70H Status output RY/BY Auto Block Erase Setup command : VIH or VIL Erase Start command Busy Status Read command : Do not input data while data is being output. 2001-05-30 13/33 TC58128AFTI ID Read Operation Timing Diagram CLE tCLS tCS tCH tCLS tCS CE tCH WE tALH ALE tALS tALH tCR tAR1 RE tDS tDH I/O1 to I/O8 90H 00 tREAID 98H tREAID 73H Address input Maker code Device code : VIH or VIL 2001-05-30 14/33 TC58128AFTI PIN FUNCTIONS The device is a serial access memory which utilizes time-sharing input of address information. The device pin-outs are configured as shown in Figure 1. Command Latch Enable: CLE The CLE input signal is used to control loading of the operation mode command into the internal command register. The command is latched into the command register from the I/O port on the rising edge of the WE signal while CLE is High. NC NC NC NC NC GND RY/BY RE NC NC VCC VSS NC NC CLE ALE WE WP CE Address Latch Enable: ALE The ALE signal is used to control loading of either address information or input data into the internal address/data register. Address information is latched on the rising edge of WE if ALE is High. Input data is latched if ALE is Low. NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC NC NC I/O8 I/O7 I/O6 I/O5 NC NC NC VCC VSS NC NC NC I/O4 I/O3 I/O2 I/O1 NC NC NC NC Chip Enable: CE Figure 1. Pinout The device goes into a low-power Standby mode when CE goes High during a Read operation. The CE signal is ignored when device is in Busy state ( RY/ BY = L), such as during a Program or Erase operation, and will not enter Standby mode even if the CE input goes High. The CE signal must stay Low during the Read mode Busy state to ensure that memory array data is correctly transferred to the data register. Write Enable: WE The WE signal is used to control the acquisition of data from the I/O port. Read Enable: RE The RE signal controls serial data output. Data is available tREA after the falling edge of RE . The internal column address counter is also incremented (Address = Address + l) on this falling edge. I/O Port: I/O1 to 8 The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from the device. Write Protect: WP The WP signal is used to protect the device from accidental programming or erasing. The internal voltage regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off sequence when input signals are invalid. Ready/Busy: RY/BY The RY/ BY output signal is used to indicate the operating condition of the device. The RY/ BY signal is in Busy state ( RY/ BY = L) during the Program, Erase and Read operations and will return to Ready state ( RY/ BY = H) after completion of the operation. The output buffer for this signal is an open drain. 2001-05-30 15/33 TC58128AFTI Schematic Cell Layout and Address Assignment The Program operation works on page units while the Erase operation works on block units. I/O1 512 16 I/O8 A page consists of 528 bytes in which 512 bytes are used for main memory storage and 16 bytes are for redundancy or for other uses. 1 page = 528 bytes 1 block = 528 bytes x 32 pages = (16K + 512) bytes Capacity = 528 bytes x 32 pages x 1024 blocks An address is read in via the I/O port over three consecutive clock cycles, as shown in Table 1. 32 pages = 32768 pages 1024 blocks = 8I/O 528 Figure 2. Schematic Cell Layout Table 1. Addressing I/O8 First cycle Second cycle Third cycle *: *: A7 A16 *L I/O7 A6 A15 A23 I/O6 A5 A14 A22 I/O5 A4 A13 A21 I/O4 A3 A12 A20 I/O8 must be set to Low in the third cycle. Table 2. Logic table CLE Command Input Data Input Address Input Serial Data Output During Programming (Busy) During Erasing (Busy) Program, Erase Inhibit H: VIH, L: VIL, *: VIH or VIL H L L L * * * 1 block I/O3 A2 A11 A19 I/O2 A1 A10 A18 I/O1 A0 A9 A17 A0~A7: A9~A23: A14~A23: A9~A13: Column address Page address Block address NAND address in block A8 is automatically set to Low or High by a 00H command or a 01H command. Operation Mode: Logic and Command Tables The operation modes such as Program, Erase, Read and Reset are controlled by the ten different command operations shown in Table 3. Address input, command input and data input/output are controlled by the CLE, ALE, CE , WE , RE and WP signals, as shown in Table 2. ALE L L H L * * * CE WE RE WP L L L L * * * H * * * H H H * * * * * * * H H L 2001-05-30 16/33 TC58128AFTI Table 3. Command table (HEX) First Cycle Serial Data Input Read Mode (1) Read Mode (2) Read Mode (3) Reset Auto Program Auto Block Erase Status Read ID Read 80 00 01 50 FF 10 60 70 90 Second Cycle D0 Q Q 1 0 0 6 0 5 0 4 0 3 0 0 Acceptable while Busy HEX data bit assignment (Example) Serial data input: 80H I/O8 7 2 I/O1 Once the device has been set to Read mode by a 00H, 01H or 50H command, additional Read commands are not needed for sequential page Read operations. Table 4 shows the operation states for Read mode. Table 4. Read mode operation states CLE Output Select Output Deselect Standby H: VIH, L: VIL, *: VIH or VIL L L L ALE L L L CE WE RE I/O1~I/O8 Data output High impedance High impedance Power Active Active Standby L L H H H H L H * 2001-05-30 17/33 TC58128AFTI DEVICE OPERATION Read Mode (1) Read mode (1) is set when a 00H command is issued to the Command register. Refer to Figure 3 below for timing details and the block diagram. CLE CE WE ALE RE RY/BY M I/O 00H N Busy Start-address input M Select page N Figure 3. Read mode (1) operation 527 A data transfer operation from the cell array to the register starts on the rising edge of WE in the third cycle (after the address information has been latched). The device will be in Busy state during this transfer period. The CE signal must stay Low after the third address input and during Busy state. After the transfer period the device returns to Ready state. Serial data can be output synchronously with the RE clock from the start pointer designated in the address input cycle. Cell array Read Mode (2) CLE CE WE ALE RE RY/BY M I/O 01H N Busy Start-address input 256 Select page N Figure 4. Read mode (2) operation M 527 The operation of the device after input of the 01H command is the same as that of Read mode (1). If the start pointer is to be set after column address 256, use Read mode (2). However, for a Sequential Read, output of the next page starts from column address 0. Cell array 2001-05-30 18/33 TC58128AFTI Read Mode (3) Read mode (3) has the same timing as Read modes (1) and (2) but is used to access information in the extra 16-byte redundancy area of the page. The start pointer is therefore set to a value between byte 512 and byte 527. CLE CE WE ALE RE RY/BY Busy 50H A0~A3 512 527 Addresses bits A0~A3 are used to set the start pointer for the redundant memory cells, while A4~A7 are ignored. Once a 50H command has been issued, the pointer moves to the redundant cell locations and only those 16 cells can be addressed, regardless of the value of the A4-to-A7 address. (An 00H command is necessary to move the pointer back to the 0-to-511 main memory cell location.) I/O Figure 5. Read mode (3) operation Sequential Read (1) (2) (3) This mode allows the sequential reading of pages without additional address input. 00H 01H 50H RY/BY Address input tR Busy Data output tR Busy Data output tR Busy (00H) 0 527 (01H) (50H) 512 527 A A A Sequential Read (1) Sequential Read (2) Sequential Read (3) Sequential Read modes (1) and (2) output the contents of addresses 0~527 as shown above, while Sequential Read mode (3) outputs the contents of the redundant address locations only. When the pointer reaches the last address, the device continues to output the data from this address ** on each RE clock signal. ** Column address 527 on the last page. 2001-05-30 19/33 TC58128AFTI Status Read The device automatically implements the execution and verification of the Program and Erase operations. The Status Read function is used to monitor the Ready/Busy status of the device, determine the result (pass/fail) of a Program or Erase operation, and determine whether the device is in Protect mode. The device status is output via the I/O port on the RE clock after a 70H command input. The resulting information is outlined in Table 5. Table 5. Status output table STATUS I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 Pass/Fail Not Used Not Used Not Used Not Used Not Used Ready/Busy Write Protect Pass: 0 0 0 0 0 0 Ready: 1 Protect: 0 Busy: 0 Not Protected: 1 The Pass/Fail status on I/O1 is only valid when the device is in the Ready state. OUTPUT Fail: 1 An application example with multiple devices is shown in Figure 6. CE1 CE2 CE3 CEN CEN + 1 CLE ALE WE RE I/O1 ~I/O8 RY/BY RY/BY Device 1 Device 2 Device 3 Device N Device N+1 Busy CLE ALE WE CE1 CEN RE I/O 70H Status on Device 1 70H Status on Device N Figure 6. Status Read timing application example System Design Note: If the RY/ BY pin signals from multiple devices are wired together as shown in the diagram, the Status Read function can be used to determine the status of each individual device. 2001-05-30 20/33 TC58128AFTI Auto Page Program The device carries out an Automatic Page Program operation when it receives a "10H" Program command after the address and data have been input. The sequence of command, address and data input is shown below. (Refer to the detailed timing chart.) 80 10 70 Status Read command I/O Pass Data input Address Data input Program command input 0 to 527 command Fail RY/BY RY/BY automatically returns to Ready after completion of the operation. Data input Program Selected page Reading & verification The data is transferred (programmed) from the register to the selected page on the rising edge of WE following input of the "10H" command. After programming, the programmed data is transferred back to the register to be automatically verified by the device. If the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. Figure 7. Auto Page Program operation Auto Block Erase The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command "D0H" which follows the Erase Setup command "60H". This two-cycle process for Erase operations acts as an ertra layer of protection from aceidental erasure of data due to external noise. The device automatically executes the Erase and Verify operations. Pass 60 D0 Block Address Erase Start input: 2 cycles command 70 Status Read command Busy I/O Fail RY/BY 2001-05-30 21/33 TC58128AFTI Reset The Reset mode stops all operations. For example, in the case of a Program or Erase operation the internally generated voltage is discharged to 0 volts and the device enters Wait state. The response to an "FFH" Reset command input during the various device operations is as follows: When a Reset (FFH) command is input during programming Figure 8. 80 Internal VPP RY/BY 10 FF 00 tRST (max 10 s) When a Reset (FFH) command is input during erasing Figure 9. D0 Internal erase voltage RY/BY FF 00 tRST (max 500 s) When a Reset (FFH) command is input during Read operation Figure 10. 00 RY/BY FF 00 tRST (max 6 s) When a Status Read command (70H) is input after a Reset Figure 11. FF RY/BY 70 I/O status: Pass/Fail Pass Ready/Busy Ready FF RY/BY 70 I/O status: Ready/Busy Busy When two or more Reset commands are input in succession Figure 12. (1) FF RY/BY (2) FF (3) FF The second FF command is invalid, but the third FF command is valid. 2001-05-30 22/33 TC58128AFTI ID Read The TC58128A contains ID codes which identify the device type and the manufacturer. The ID codes can be read out under the following timing conditions: CLE tCR CE WE tAR1 ALE RE tREAID I/O 90H ID Read command 00 Address 00 98H Maker code 73H Device code For the specifications of the access times tREAID, tCR and tAR1 refer to the AC Characteristics. Figure 13. ID Read timing Table 6. ID Codes read out by ID read command 90H I/O8 Maker code Device code 1 0 I/O7 0 1 I/O6 0 1 I/O5 1 1 I/O4 1 0 I/O3 0 0 I/O2 0 1 I/O1 0 1 Hex Data 98H 73H 2001-05-30 23/33 TC58128AFTI APPLICATION NOTES AND COMMENTS (1) Power-on/off sequence: The WP signal is useful for protecting against data corruption at power-on/off. The following timing sequence is necessary. The WP signal may be negated any time after the VCC reaches 2.5 V and CE signal is kept high in power up sequence. 2.7 V 2.5 V 0V VCC Don't care CE , WE , RE CLE, ALE Don't care VIH WP VIL Operation Figure 15. Power-on/off Sequence VIL In order to operate this device stably, after VCC becomes 2.5 V, it recommends starting access after about 200 s. (2) Status after power-on The following sequence is necessary because some input signals may not be stable at power-on. Power on FF Reset Figure 16. (3) Prohibition of unspecified commands The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle. (4) Restriction of command while Busy state During Busy state, do not input any command except 70H and FFH. (5) Acceptable commands after Serial Input command "80H" Once the Serial Input command "80H" has been input, do not input any command other than the Program Execution command "10H" or the Reset command "FFH". If a command other than "10H" or "FFH" is input, the Program operation is not performed. 80 XX 10 Programming cannot be executed. For this operation the "FFH" command is needed. Command other than "10H" or "FFH" 2001-05-30 24/33 TC58128AFTI (6) Addressing for program operation Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most significant bit) page of the block. Random page address programming is prohibited. From the LSB page to MSB page DATA IN: Data (1) Data (32) Data register Page 0 Page 1 Page 2 (1) (2) (3) Page 0 Page 1 Page 2 Ex.) Random page program (Prohibition) DATA IN: Data (1) Data (32) Data register (2) (16) (3) Page 15 (16) Page 15 (1) Page 31 (32) Page 31 Figure 17. page programming within a block (32) (7) Status Read during a Read operation 00 command CE WE RY/BY RE 00 70 [A] Address N Status Read command input Figure 18. Status Read Status output The device status can be read out by inputting the Status Read command "70H" in Read mode. Once the device has been set to Status Read mode by a "70H" command, the device will not return to Read mode. Therefore, a Status Read during a Read operation is prohibited. However, when the Read command "00H" is input during [A], Status mode is reset and the device returns to Read mode. In this case, data output starts automatically from address N and address input is unnecessary 2001-05-30 25/33 TC58128AFTI (8) Pointer control for "00H", "01H" and "50H" The device has three Read modes which set the destination of the pointer. Table 7 shows the destination of the pointer, and Figure 14 is a block diagram of their operations. Table 8. Pointer Destination Read Mode (1) (2) (3) Command 00H 01H 50H Pointer 0 to 255 256 to 511 512 to 527 (1) 00H (2) 01H (3) 50H Pointer control Figure 19. Pointer control 0 A 255 256 B 511 512 527 C The pointer is set to region A by the "00H" command, to region B by the "01H" command, and to region C by the "50H" command. (Example) The "00H" command must be input to set the pointer back to region A when the pointer is pointing to region C. 00H Add Start point A area Add Start point A area 00H Add Start point C area Add Start point C area Add Start point A area 50H Add Start point C area 50H 01H Add Start point B area Add Start point A area To program region C only, set the start point to region C using the 50H command. 50H 80H Add DIN Start point C Area 10H Programming region C only 01H 80H Add DIN Start point B Area 10H Programming region B and C Figure 20. Example of How to Set the Pointer 2001-05-30 26/33 TC58128AFTI (9) RY/ BY : termination for the Ready/Busy pin ( RY/ BY ) A pull-up resistor needs to be used for termination because the RY/ BY buffer consists of an open drain circuit. VCC VCC Device CL VSS Figure 21. tr This data may vary from device to device. We recommend that you use this data as a reference when selecting a resistor value. 1.5 s 1.0 s 0.5 s 0 1 K tr tf R RY/BY Ready 3.0 V VCC 1.0 V tf Busy 1.0 V tr VCC = 3.3 V Ta = 25C CL = 100 pF 3.0 V 15 ns 10 ns 5 ns tf 2 K R 3 K 4 K 2001-05-30 27/33 TC58128AFTI (10) Note regarding the WP signal The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming WE DIN WP RY/BY 80 10 tWW (100 ns min) Disable Programming WE DIN WP RY/BY 80 10 tWW (100 ns min) Enable Erasing WE DIN WP RY/BY 60 D0 tWW (100 ns min) Disable Erasing WE DIN WP RY/BY 60 D0 tWW (100 ns min) 2001-05-30 28/33 TC58128AFTI (11) When four address cycles are input Although the device may read in a fourth address, it is ignored inside the chip. Read operation CLE CE WE ALE I/O 00H, 01H, 50H RY/BY Address input Ignored Internal read operation starts when WE goes High in the third cycle. Figure 22. Program operation CLE CE WE ALE I/O 80H Address input Ignored Figure 23. Data input 2001-05-30 29/33 TC58128AFTI (12) Several programming cycles on the same page (Partial Page Program) A page can be divided into up to 3 segments. Each segment can be programmed individually as follows: 1st programming Data Pattern 1 All 1s 2nd programming All 1s Data Pattern 2 All 1s nth programming All 1s Data Pattern 3 Result Data Pattern 1 Data Pattern 2 Figure 24. Data Pattern 3 Note: The input data for unprogrammed or previously programmed page segments must be "1" (i.e. the inputs for all page bytes outside the segment which is to be programmed should be set to all "1"). (13) Note regarding the RE signal RE The internal column address counter is incremented synchronously with the RE clock in Read mode. Therefore, once the device has been set to Read mode by a "00H", "01H" or "50H" command, the internal column address counter is incremented by the RE clock independently of the address input timing, If the RE clock input pulses start before the address input, and the pointer reaches the last column address, an internal read operation (array to register) will occur and the device will enter Busy state. (Refer to Figure 25.) Address input I/O 00H/01H/50H WE RE RY/BY Figure 25. Hence the RE clock input must start after the address input. 2001-05-30 30/33 TC58128AFTI (14) Invalid blocks (bad blocks) The device contains unusable blocks. Therefore, at the time of use, please check whether a block is bad and do not use these bad blocks. At the time of shipment, all data bytes in a Valid Block are FFH. For Bad Block, all bytes are not in the FFH state. Please don't perform erase operation to Bad Block. Check if the device has any bad blocks after installation into the system. Figure 27 shows the test flow for bad block detection. Bad blocks which are detected by the test flow must be managed as unusable blocks by the system. A bad block does not affect the performance of good blocks because it is isolated from the Bit line by the Select gate Bad Block Bad Block Figure 26. The number of valid blocks at the time of shipment is as follows: MIN Valid (Good) Block Number 1004 TYP. MAX 1024 UNIT Block Bad Block Test Flow Start Read Check: to verify all pages in the block with FF (Hex) Block No = 1 Read Check Pass Block No. = Block No. + 1 Fail Bad Block *1 No Block No. = 1024 Yes End *1: No erase operation is allowed to detected bad blocks Figure 27 2001-05-30 31/33 TC58128AFTI (15) Failure phenomena for Program and Erase operations The device may fail during a Program or Erase operation. The following possible failure modes should be considered when implementing a highly reliable system. FAILURE MODE Block Page Erase Failure Programming Failure Programming Failure 10 DETECTION AND COUNTERMEASURE SEQUENCE Status Read after Erase Block Replacement Status Read after Program Block Replacement (1) Block Verify after Program Retry (2) ECC Single Bit * * ECC: Error Correction Code Block Replacement Program Error occurs Buffer memory Block A When an error happens in Block A, try to reprogram the data into another Block (Block B) by loading from an external buffer. Then, prevent further system accesses to Block A (by creating a bad block table or by using an another appropriate scheme). Block B Figure 28. Erase When an error occurs in an Erase operation, prevent future accesses to this bad block (again by creating a table within the system or by using another appropriate scheme). 2001-05-30 32/33 TC58128AFTI Package Dimensions Weight: 0.53 g (typ.) 2001-05-30 33/33 |
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